Sample and hold circuits for low-frequency signals in analog-to-digital converter

Different sample and hold (S/H) circuits are introduced, analyzed and simulated in this paper. It aims to illustrate the suitable sample and hold (S/H) circuit technique that is used in low voltage operation. In addition to that, a suitable sample and hold (S/H) circuit for electrocardiogram (ECG) signal is presented. A modified versions of passive free op-amp sample and hold (S/H) circuit is discussed in order to compensate the induced error. These different sample and hold (S/H) circuits were simulated using 90nm CMOS technology on LT Spice IV. According to the simulation results, the passive free op-amp sample and hold circuit has a signal to noise and distortion ratio (SNDR) of 54.34 dB. On the other hand, the differential passive free op-amp sample and hold circuit has 56.31 dB for a 250 Hz-500 mV_p-p input sinewave and ECG signals. The sampling rate is 10 KS/sec, and the supply voltage is 1V. The simulation results show that the differential passive free op-amp sample and hold (S/H) circuit is the best candidate for low-frequency signals.