Development of a 90 nm large-scale TEG for evaluation and analysis of signal integrity, yield and variation

We have developed the 90 nm TEG (Test Element Group) that has large-scale patterns which compare well to those of a SoC(system on a chip) and has 4-corner address decoders. This TEG is based on the design rules of processes that are independent of the products. We have successfully measured process yield, failure terms, failure locations and evaluated characteristic variation in a chip. The yield of the first developed 130 nm large-scale TEG was improved successfully at this 90 nm TEG, and measured results were compared to 130 nm TEG. Stress tests and the new trial to SI (signal integrity) evaluation were also implemented. Those challenges will make the lead to the new knowledge of yield, variation and SI. With use of the electrical dimension measurement, charge-up damage, and analysis database software, this TEG will lead to help for SoC designers, manufactures and a strategic 65 nm technology.