DocumentCode
3119266
Title
A test structure to verify the robustness of silicided N+/P+ interface
Author
Lo, Cheng-Yao ; Lin, Shyue-Shyh ; Chen, Wei-Ming ; Mii, Yuh-Jier
Author_Institution
Adv. Logic-1, Logic Technol. Div., Taiwan Semicond. Manuf. Co. Ltd., Hsin-Chu, Taiwan
fYear
2004
fDate
22-25 March 2004
Firstpage
169
Lastpage
172
Abstract
We propose a new test structure that provides a single current path for silicide robustness detection at N+/P+ butted well tap interface with good sensitivity. Two reference test structures suspected with more than one current path and consequently give false results are also compared for structure and electrical performances.
Keywords
integrated circuit interconnections; integrated circuit metallisation; integrated circuit testing; leakage currents; sensitivity analysis; butted well tap interface; current leakage; electrical performance; reference structures; resistor bar; robustness verification; sensitivity; silicided N+/P+ interface; single current path; test structure; Circuits; Contacts; Implants; Logic testing; Performance evaluation; Resistors; Robustness; Semiconductor device testing; Silicides; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronic Test Structures, 2004. Proceedings. ICMTS '04. The International Conference on
Print_ISBN
0-7803-8262-5
Type
conf
DOI
10.1109/ICMTS.2004.1309473
Filename
1309473
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