Advanced architectures for current memory sigma-delta modulators

Analog to digital converters using the ΣΔ technique have been realized in switched-capacitor form to implement basic low-cost 14 to 16 bit audio data-converters, and resolutions of up to 20 bits can be achieved. Current memory based realizations have so far been disappointing, with most realizations exhibiting performances in the 10 to 12 bit range. Only recently, a 14-bit modulator has been reported. Behavioural simulations with sophisticated model have shown that the main limitations come from the inherent nonlinearity of the current memory cell, and from mismatch errors in some modulator architectures with multiple signal paths. A new architecture for ΣΔ modulators, based on an analog to digital symmetry is presented. 2nd and 3rd order modulators show promising results in terms of signal reduction in the delay cells