A fast serial Viterbi decoder ASIC for CDMA cellular base station

Author

Kong, Jun Jin ; Park, Yong Woo ; Kim, Min-Goo ; Kim, Youngky ; Jeung, Yeun-Cheul

Author_Institution

ASIC Center Corp. Tech. Operations, Samsung Electon. Co. Ltd., South Korea

Volume

1

fYear

1996

fDate

26-29 Nov 1996

Firstpage

333

Abstract

A fast serial Viterbi decoder (FSVD) ASIC for a base station channel card in IS-95 direct sequence-code division multiple access (DS-CDMA) has been developed using 0.8 μm CMOS technology of Samsung. To reduce the decoding time and store path metrics, four add-compare-select (ACS) pairs with several internal SRAMs and one external 6 K byte SRAM are used, respectively. Decoding depth of FSVD is variable to get the better coding gain. It is shown that the proposed scheme can reduce decoding time considerably more than other schemes

Keywords

CMOS digital integrated circuits; Viterbi decoding; application specific integrated circuits; cellular radio; code division multiple access; digital signal processing chips; land mobile radio; spread spectrum communication; telecommunication channels; 0.8 mum; CDMA cellular base station; CMOS technology; FSVD; IS-95 direct sequence-code division multiple access; add-compare-select pairs; base station channel card; coding gain; decoding time; external 6 K byte SRAM; fast serial Viterbi decoder ASIC; internal SRAMs; path metrics; Application specific integrated circuits; Base stations; CMOS technology; Convolutional codes; Cyclic redundancy check; Decoding; Modulation coding; Multiaccess communication; Parallel processing; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

TENCON '96. Proceedings., 1996 IEEE TENCON. Digital Signal Processing Applications

Conference_Location

Perth, WA

Print_ISBN

0-7803-3679-8

Type

conf

DOI

10.1109/TENCON.1996.608836

Filename

608836