MAC-PHY interface design and implementation based on PLB for Gbps transmission system

This paper presents an innovative interface design and its field programmable gate array (FPGA) implementation for transparent transmission between medium access control (MAC) layer and physical (PHY) layer. In the interface design, we introduce a mechanism of central process unit (CPU) and FPGA co-processing data so as to obtain good performance compared with conventional interface architecture. In addition, enhanced memory architecture, including memory separating and co-operating among different types of memory, is also taken into consideration to achieve this goal. The design uses the intellectual property (IP) core technology on processor local bus (PLB) with high throughput, low latency and low complexity. Based on a wireless transmission system with Gigabit (Gbps) throughput, the interface prototype has been implemented on Xilinx Virtex5 FX130T FPGA. The implementation results show that the interface logic can achieve a peak throughput up to 3.93 Gbps and on average to 1.02 Gbps.