Extreme scaling with ultra-thin Si channel MOSFETs

Author

Doris, Bruce ; Ieong, Meikei ; Kanarsky, Thomas ; Zhang, Ying ; Roy, Ronnen A. ; Dokumaci, Omer ; Ren, Zhibin ; Jamin, Fen-Fen ; Shi, Leathen ; Natzle, Wesley ; Huang, Hsiang-Jen ; Mezzapelle, Joseph ; Mocuta, Anda ; Womack, Sherry ; Gribelyuk, Michael ;

Author_Institution

Microelectron. Div., IBM Semicond. Res. & Dev. Center, Hopewell Junction, NY, USA

fYear

2002

fDate

8-11 Dec. 2002

Firstpage

267

Lastpage

270

Abstract

We examine the scaling limits for planar single gate technology using the ultra-thin Si channel MOSFET. Characteristics for extreme scaled devices with physical gate lengths down to 6 nm and SOI channels as thin as 4 nm are presented. For the first time, we report ring oscillators with 26 nm gate lengths and ultra-thin Si channels.

Keywords

CMOS integrated circuits; MOSFET; elemental semiconductors; nanoelectronics; silicon; silicon-on-insulator; 14 nm; 4 to 26 nm; CMOS device scaling; SCE control; SOI channels; SOI wafers; Si; extreme scaling; planar single gate technology; scaling limits; short channel effect; thick gate oxide; ultra-thin Si channel MOSFETs; Dielectrics; Doping; Fabrication; Implants; MOSFETs; Microelectronics; Oxidation; Research and development; Ring oscillators; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2002. IEDM '02. International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7462-2

Type

conf

DOI

10.1109/IEDM.2002.1175829

Filename

1175829

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3128657