• DocumentCode
    3128812
  • Title

    Multiprocessor Task Migration Implementation in a Reconfigurable Platform

  • Author

    Gantel, L. ; Layouni, S. ; Benkhelifa, M. E A ; Verdier, F. ; Chauvet, S.

  • Author_Institution
    ENSEA, Univ. of Cergy-Pontoise, Cergy-Pontoise, France
  • fYear
    2009
  • fDate
    9-11 Dec. 2009
  • Firstpage
    362
  • Lastpage
    367
  • Abstract
    Mutiprocessor architecture in embedded computing is becoming widely used. In fact, with specific development tools, platforms such as Xilinx Virtex-5 or Virtex-6 FPGA can implement multiprocessor systems (with soft-core and hard-core processors) {with just a few mouse clicks} and offer the possibility of partial and dynamic reconfiguration. Software tasks are scheduled on these platforms by embedded and distributed Real Time Operating System (RTOS). To provide high performance (execution time, power consumption...) to these Multiprocessor Soc (MPSoC) platforms, the RTOS can enable the migration of software tasks between processors. Our work deals with the study and the development of a software layer (an application programming interface) which allows task migration between soft-core processors. The soft-core can be dynamically loaded on FPGA on demand. In this paper, we present a platform that merges these two aspects, partial reconfiguration and software task migration in the context of MPSoCs. We notably investigate the incurred time and overhead for task migration and partial reconfiguration.
  • Keywords
    application program interfaces; microcomputers; power aware computing; processor scheduling; reconfigurable architectures; system-on-chip; task analysis; MPSoC platform; Virtex-6 FPGA; Xilinx Virtex-5; application programming interface; distributed real time operating system; dynamic reconfiguration; execution time; hard-core processor; multiprocessor SoC; multiprocessor task migration implementation; partial reconfiguration; power consumption; reconfigurable platform; soft-core processor; software task migration; Computer architecture; Embedded computing; Embedded software; Energy consumption; Field programmable gate arrays; Mice; Multiprocessing systems; Operating systems; Processor scheduling; Real time systems; Dynamic and partial reconfigurable systems; FPGA; MPSoC; RTOS for embedded platforms; Task migration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Reconfigurable Computing and FPGAs, 2009. ReConFig '09. International Conference on
  • Conference_Location
    Quintana Roo
  • Print_ISBN
    978-1-4244-5293-4
  • Electronic_ISBN
    978-0-7695-3917-1
  • Type

    conf

  • DOI
    10.1109/ReConFig.2009.37
  • Filename
    5382087