• DocumentCode
    3129361
  • Title

    Multi-scale measurement of the change of the residual stress in a silicon chip during manufacturing from thin-film processing to packaging

  • Author

    Kishi, Hirko ; Sasaki, Takuya ; Ueta, Nobuki ; Suzuki, Ken ; Miura, Hideo

  • Author_Institution
    Dept. of Nanomech., Tohoku Univ., Sendai, Japan
  • fYear
    2009
  • fDate
    21-23 Oct. 2009
  • Firstpage
    293
  • Lastpage
    296
  • Abstract
    Both thermal and intrinsic stresses that occur during thin-film processing and packaging dominate the final residual stress in thin film electronic devices. Since the residual stress causes the shift of electronic functions of dielectric and semiconductor materials, these shifts sometimes degrade their performance and reliability. Therefore, it is very important to measure and control the residual stress in thin-film-applied products. In this study, the changes of the electronic performance of MOS transistors by mechanical stress were measured by applying a four-point bending method. The stress sensitivity of the transconductance of NMOS transistors increased from about 1%/100-MPa to about 15%/100-MPa by decreasing the gate length of the transistors from 400 nm to 150 nm. So, it showed miniaturization of transistors increased the stress sensitivity of the performance. One of the estimated important factors which dominated this increase was attributed to the interference of stress concentration fields occurred at the edges of gate electrodes. The change of the residual stress in a transistor structure caused by deposition of thin films was analyzed by applying a finite element method (FEM). The estimated change was validated by experiment using originally developed stress sensing chips. The estimated change of the stress due to deposition of gate electrode tungsten film was about 25MPa. The measured average stress was about 20MPa and it agreed well with the estimated value. Next, the change of the residual stress caused by the interference of the stress concentration field between gate-electrodes was validated by applying this stress sensing chip. The measured change of the stress caused by making one slit by focused ion beam was about 70MPa and it agreed well with the estimated value of about 60MPa. In addition, the change of residual stress was increased with the more decreased width of slits. It was confirmed, therefore, that both the thin film process-induced str- ess and the packaging-induced stress change the final residual stress in a transistor structure and the change can be evaluated by our stress-sensing chip quantitatively.
  • Keywords
    MOS integrated circuits; finite element analysis; integrated circuit manufacture; integrated circuit packaging; integrated circuit testing; internal stresses; semiconductor technology; thermal stresses; FEM; MOS transistors; NMOS transistor transconductance; finite element method; four point bending method; gate electrodes; integrated circuit packaging; intrinsic stress; packaging induced stress; process induced stress; residual stress; silicon chip; stress sensing chip; stress sensitivity; thermal stress; thin film processing; Dielectric thin films; Electronic packaging thermal management; Manufacturing processes; Residual stresses; Semiconductor device measurement; Semiconductor device packaging; Semiconductor thin films; Silicon; Stress measurement; Thin film transistors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microsystems, Packaging, Assembly and Circuits Technology Conference, 2009. IMPACT 2009. 4th International
  • Conference_Location
    Taipei
  • Print_ISBN
    978-1-4244-4341-3
  • Electronic_ISBN
    978-1-4244-4342-0
  • Type

    conf

  • DOI
    10.1109/IMPACT.2009.5382116
  • Filename
    5382116