DocumentCode
3129398
Title
A novel 0.79 /spl mu/m/sup 2/ SRAM cell by KrF lithography and high performance 90 nm CMOS technology for ultra high speed SRAM
Author
Soon-Moon Jung ; Hyungshin Kwon ; Jaehun Jeong ; Wonseok Cho ; Sungbong Kim ; Hoon Lim ; Kwangok Koh ; Youngseop Rah ; Jaekyun Park ; Heesoo Kang ; Gyuho Lyu ; Joonbum Park ; Chulsoon Chang ; Youngchul Jang ; Donggun Park ; Kinam Kim ; Moon Yong Lee
Author_Institution
Adv. Technol. Dev. Team, Samsung Electron. Co. Ltd., South Korea
fYear
2002
fDate
8-11 Dec. 2002
Firstpage
419
Lastpage
422
Abstract
The smallest SRAM cell, 0.79 /spl mu/m/sup 2/, was realized by a revolutionary cell layout, fine tuned OPC technique to overcome the 248 nm KrF lithography limitation, instead of using 193 nm ArF lithography. Sub-100 nm CMOS technology was indispensable to achieve the cell size as well as the performance. The high performance transistors were made with 80 nm gate length including 15 /spl Aring/ nitrided gate oxide layer, indium channel and halo implantation processes. The novel cell exhibits excellent neutron SER immunity, compared with ones of the SRAM cell by previous generation technologies.
Keywords
CMOS memory circuits; SRAM chips; high-speed integrated circuits; integrated circuit layout; ion implantation; neutron effects; proximity effect (lithography); ultraviolet lithography; 15 A; 248 nm; 80 nm; 80 nm gate length; 90 nm; CMOS SRAM cell; In channel; KrF lithography; cell layout; cell size; fine tuned OPC technique; halo implantation processes; high performance 90 nm CMOS technology; high performance transistors; neutron SER immunity; nitrided gate oxide layer; ultra high speed SRAM; CMOS technology; Flash memory; Indium; Lithography; Moon; Neutrons; Random access memory; Research and development; Resists; Space technology;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 2002. IEDM '02. International
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-7462-2
Type
conf
DOI
10.1109/IEDM.2002.1175868
Filename
1175868
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