Multiplier block synthesis using evolutionary graph generation

This paper presents a graph-based evolutionary optimization technique, called evolutionary graph generation (EGG), and its application to hierarchical synthesis of arithmetic circuits. In stead of creating bit-level circuits directly, the EGG system generates arithmetic data-flow graphs that can be transformed into actual bit-level circuit configurations. The potential capability of EGG has been investigated through an experiment of synthesizing multiplier blocks which are used in many DSP applications.