Quantum tunneling and scalability of HfO2 and HfAlO gate stacks

We present a physical model for tunneling current through high-/spl kappa/ gate stacks including an ultra thin interfacial layer between high-/spl kappa/ layers and the Si substrate. The energy band offsets of high-/spl kappa/ are determined by XPS. Accurate carrier quantization in the substrate or gate is found to play a more significant role in tunneling through high-/spl kappa/ dielectrics than in SiO/sub 2/. Excellent agreement between simulated and measured tunneling currents is achieved over several high-/spl kappa/ dielectrics with both poly-Si and metal gate electrodes. The model is also applied to analyze the scalability of HfO/sub 2/ and HfAlO gate stacks in future CMOS technology.