DocumentCode
3131466
Title
A capacitorless double-gate DRAM cell design for high density applications
Author
Kuo, C. ; Tsu-Jae King ; Chenming Hu
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fYear
2002
fDate
8-11 Dec. 2002
Firstpage
843
Lastpage
846
Abstract
Experimental measurements and 2-D device simulation are used to investigate a capacitorless, asymmetric double-gate DRAM (DG-DRAM) design. Soft error problems are discussed. Careful attention to cell geometry and film quality results in intrinsic retention times suitable for stand-alone and embedded memories.
Keywords
CMOS memory circuits; DRAM chips; MOSFET; integrated circuit design; radiation hardening (electronics); silicon-on-insulator; 2-D device simulation; CMOS memory technologies; capacitorless asymmetric double-gate DRAM design; capacitorless double-gate DRAM cell design; cell geometry; embedded memories; film quality; fully depleted SOI MOSFET; high density applications; intrinsic retention times; recessed channel SOI process; soft error problems; stand-alone memories; Back; Capacitors; Doping profiles; MOSFET circuits; Random access memory; Semiconductor films; Silicon; Substrates; Threshold voltage; Tunneling;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 2002. IEDM '02. International
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-7462-2
Type
conf
DOI
10.1109/IEDM.2002.1175969
Filename
1175969
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