15-nm-thick Si channel wall vertical double-gate MOSFET

Author

Masahara, Meishoku ; Matsukawa, Takashi ; Ishii, Ken-ichi ; Liu, Yongxun ; Tanoue, Hisao ; Sakamoto, Kunihiro ; Sekigawa, Toshihiro ; Yamauchi, Hiromi ; Kanemaru, Seigo ; Suzuki, Eiichi

Author_Institution

Nanoelectronics Res. Inst., Nat. Inst. of Adv. Ind. Sci. & Technol., Tsukuba, Japan

fYear

2002

fDate

8-11 Dec. 2002

Firstpage

949

Lastpage

951

Abstract

Double-gate (DG) MOSFET structures have been regarded as promising candidates for scalable CMOS devices. Among DG concept devices, a vertical type has attracted considerable attention due to its process compatibility with conventional CMOS technology and its suitability with bulk Si substrates. The critical issue is fabrication technology, especially for the ultra-thin Si wall for the vertical transistor. This paper demonstrates, for the first time, vertical DG MOSFETs (´IMOSFETs´) with a 15-nm-thick channel wall fabricated by using the newly-discovered ion-bombardment-retarded etching (IBRE) of Si in a tetramethylammonium hydroxide (TMAH) solution.

Keywords

MOSFET; elemental semiconductors; etching; ion beam effects; silicon; 15 nm; CMOS device; IMOSFET; Si; Si channel wall; TMAH solution; fabrication technology; ion-bombardment-retarded etching; vertical double-gate MOSFET; CMOS process; CMOS technology; Conductivity; Contact resistance; Erbium; Fabrication; Ion beams; Ion implantation; MOSFET circuits; Wet etching;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2002. IEDM '02. International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7462-2

Type

conf

DOI

10.1109/IEDM.2002.1175994

Filename

1175994