DocumentCode
3132297
Title
Yield optimization in the mature fab
Author
Effron, Melvyn ; Carlson, Bob ; Hiscock, David
Author_Institution
HPL Corp. Inc., San Jose, CA, USA
fYear
2001
fDate
2001
Firstpage
193
Lastpage
200
Abstract
This paper provides the authors´ insights and discussions in four areas of yield optimization available to the mature semiconductor fabricator. The mature fab is arbitrarily defined as fabs older than 3 years having feature sizes of >0.5 μm. The areas of yield optimization include: (1) cost and implementation considerations for an integrated data collection and information analysis system; (2) use of a quantified and partitioned D0 yield model; (3) focus on baseline yield quantification and improvement practices versus excursion controls; (4) increased roles and responsibilities for yield improvement
Keywords
circuit optimisation; data acquisition; data analysis; fault location; integrated circuit testing; integrated circuit yield; production testing; baseline yield quantification; cost considerations; excursion controls; feature sizes; implementation considerations; integrated data collection/information analysis system; mature fab; mature semiconductor fabricator; quantified partitioned yield model; yield improvement; yield optimization; Cost function; Data systems; Demography; Fabrication; Investments; Manufacturing automation; Probes; Productivity; Robustness; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced Semiconductor Manufacturing Conference, 2001 IEEE/SEMI
Conference_Location
Munich
ISSN
1078-8743
Print_ISBN
0-7803-6555-0
Type
conf
DOI
10.1109/ASMC.2001.925646
Filename
925646
Link To Document