Efficient implementation of MPEG video codec using dual processors

Author

Sankar, V. ; Srinivasan, S. ; Rangarajan, S.R.

Author_Institution

Dept. of Electr. Eng., Indian Inst. of Technol., Madras, India

Volume

2

fYear

1997

fDate

2-4 Jul 1997

Firstpage

801

Abstract

Presented here is a parallel processing system based on a digital signal processor (DSP) and a PC-AT host processor to increase the computational speed of the MPEG compression algorithm. The algorithm is split into independent tasks of approximately the same complexity, allocated to the DSP and the host processor based on the relative merits of the tasks, and computed concurrently, resulting in a twofold increase in speed. Furthermore, a provision is made to enable the user to effect a compression-quality tradeoff

Keywords

computational complexity; digital signal processing chips; parallel processing; video codecs; video coding; DSP; MPEG compression algorithm; MPEG video codec; PC-AT host processor; compression-quality tradeoff; computational speed; digital signal processor; dual processors; parallel processing system; Compression algorithms; Concurrent computing; Digital signal processing; Discrete cosine transforms; Entropy coding; Quantization; Signal processing algorithms; Transform coding; Video codecs; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

Digital Signal Processing Proceedings, 1997. DSP 97., 1997 13th International Conference on

Conference_Location

Santorini

Print_ISBN

0-7803-4137-6

Type

conf

DOI

10.1109/ICDSP.1997.628474

Filename

628474