DocumentCode
3133462
Title
Design space exploration and synthesis for digital signal processing algorithms from Simulink models
Author
Butt, Shahzad Ahmad ; Lavagno, L.
Author_Institution
Dept. of Electron. & Telecommun., Politec. di Torino, Turin, Italy
fYear
2013
fDate
16-18 Dec. 2013
Firstpage
1
Lastpage
6
Abstract
Design teams are increasingly looking for design flows that can rapidly lead to high performance and low power implementation of DSP algorithms. Model-based design can satisfy this requirement, but it must be (1) coupled with efficient high-level synthesis support in order to provide good Quality of Results, and (2) controlled to derive the desired area/performance/throughput trade-off. We present a semi-automatic design flow for rapid high level synthesis-based hardware design space exploration starting from Simulink digital signal processing models. We illustrate our flow with a realistically complex signal processing algorithm for estimating the direction of arrival of a sound source. We show how one can start from a functionally validated fixed point model in Simulink and then go through a relatively simple design flow for hardware synthesis and automatic design space exploration, obtaining a very efficient hardware implementation that is competitive with the RTL implementation generated by another commercial model-based design tool.
Keywords
direction-of-arrival estimation; field programmable gate arrays; high level synthesis; DOA estimation; DSP algorithm; RTL implementation; automatic design space exploration; digital signal processing algorithm; direction of arrival; hardware synthesis; high level synthesis-based hardware design space exploration; simulink model; sound source; Algorithm design and analysis; Hardware; High level synthesis; Signal processing algorithms; Software packages; Space exploration; Throughput; Model-based hardware design; automatic high level synthesis; design space exploration; digital signal processing; direction of arrival (DOA) estimation; hardware imple-mentation; high level synthesis; model partitioning; simulink modeling;
fLanguage
English
Publisher
ieee
Conference_Titel
Design and Test Symposium (IDT), 2013 8th International
Conference_Location
Marrakesh
Type
conf
DOI
10.1109/IDT.2013.6727109
Filename
6727109
Link To Document