Comparative Analysis of High Speed and Low Area Architectures of Blake SHA-3 Candidate on FPGA

On Nov. 2, 2007, NIST announced a public competition to develop a new cryptographic hash algorithm SHA-3. After long run selection process, five finalists were selected for Round 3. Winner of this competition will be announced later in 2012. Blake is one of the candidates of round three of this competition. Along with the strength of security, efficient hardware implementation is also major evaluation criteria for final selection. Blake algorithm compression function is based on G-Function which executes 8 times in one round. In this paper, different architecture schemes named as 8G, 4G and 1G has been implemented on FPGA, based on serialization of Round Function processes. Optimization is performed by selecting appropriate numbers of LUTs and Slice Registers according to the Virtex 5 Device Architecture Resources. Implementation results of each design are compared with each other and with other design contributions. Full autonomous design for each scheme is implemented on Virtex 5 xc5vlx50t-3 FPGA. Common I/O and control interface is provided to find out the fair comparison results. For tradeoff analysis three design optimization techniques based on ´area´, ´speed´ and ´balance´ designs are used. We found 8G architecture provides the best through-put, 1G provides least area implementation and 4G provides the most efficient results in terms of throughput per area (TPA). 4G design gives Tpa of 2.1. Our design methodology and optimization strategy gives improved results from previous contributions.