HW/SW Codesign of the H. 263 Video Coder

In this paper, we propose an optimized real-time H.263 video coder. The coder has been implemented in one FPGA device as HW/SW partitioned system. We made time analysis and optimization of the H.263 coder. On the basis of the achieved results, we decided for hardware implementation of the discrete cosine transform (DCT).Remaining parts were realized in software with NIOS II softcore processor. H.263 coder (NIOS II processor, DCT core) has described by the VHDL language and implemented in Stratix EP1S10 FPGA. Finally, the coder has been tested on the Altera Stratix development board.