DocumentCode
3141623
Title
A 50-GS/s 5-b ADC in 0.18-um SiGe BiCMOS
Author
Lee, Jeyull ; Chen, Yuanfeng
Author_Institution
Alcatel-Lucent, Murray, NJ, USA
fYear
2010
fDate
23-28 May 2010
Firstpage
1
Lastpage
1
Abstract
A 5-b 50-GS/s ADC is presented in 0.18-um SiGe BiCMOS. The two-channel interleaved flash architecture is used to increase the conversion rate. The front-end three-stage distributed track-and-hold amplifier is devised to improve the dynamic performance. The ADC features SNDR as high as 23.1 dB with 20 GHz sine wave input at 50 GS/s conversion rate, and the third harmonic distortion is -36.5 dBc. It shows the measured resolution bandwidth of 18 GHz and the FOM of 9 pJ per conversion step with power consumption of 5.4 W.
Keywords
BiCMOS integrated circuits; analogue-digital conversion; distributed amplifiers; sample and hold circuits; ADC; SiGe; SiGe BiCMOS; bandwidth 18 GHz; front-end three-stage distributed track-and-hold amplifier; power 5.4 W; two-channel interleaved flash architecture; BiCMOS integrated circuits; Distributed amplifiers; Germanium silicon alloys; Harmonic distortion; Optical amplifiers; Optical fiber communication; Optical signal processing; Photonics; Silicon germanium; Wireless communication;
fLanguage
English
Publisher
ieee
Conference_Titel
Microwave Symposium Digest (MTT), 2010 IEEE MTT-S International
Conference_Location
Anaheim, CA
ISSN
0149-645X
Print_ISBN
978-1-4244-6056-4
Electronic_ISBN
0149-645X
Type
conf
DOI
10.1109/MWSYM.2010.5517519
Filename
5517519
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