DocumentCode
3142476
Title
Low-power GPS receiver design
Author
Meng, Teresa H.
Author_Institution
Dept. of Electr. Eng., Stanford Univ., CA, USA
fYear
1998
fDate
8-10 Oct 1998
Firstpage
1
Lastpage
10
Abstract
This paper describes the design of a low-power global positioning system (GPS) receiver implemented in CMOS technology. The primary GPS ranging signal is broadcast at a frequency of 1.575 GHz, modulated by a pseudo-noise sequence at a chip rate of 1 MHz. The design of this low-power GPS receiver emphasizes the circuit techniques and architectural trade-offs employed in minimizing the energy needed for each position estimate
Keywords
CMOS integrated circuits; Global Positioning System; binary sequences; distance measurement; modulation coding; pseudonoise codes; radio receivers; 1.575 GHz; CMOS technology; GPS; global positioning system; low-power receiver; pseudo-noise sequence modulation; ranging signal; Broadcasting; CMOS technology; Circuits; Clocks; Degradation; Delay; Frequency; Global Positioning System; Military satellites; Modulation coding; Phase measurement; Satellite broadcasting; Synchronization;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Processing Systems, 1998. SIPS 98. 1998 IEEE Workshop on
Conference_Location
Cambridge, MA
ISSN
1520-6130
Print_ISBN
0-7803-4997-0
Type
conf
DOI
10.1109/SIPS.1998.715763
Filename
715763
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