DocumentCode
3142836
Title
Recent advances in TRON-spec. chips
Author
Tomisawa, Osamu
Author_Institution
LSI Lab., Mitsubishi Electric Corp., Hyogo, Japan
fYear
1991
fDate
21-27 Nov 1991
Firstpage
178
Lastpage
184
Abstract
Six microprocessor chips were implemented taking the TRON architecture. Efforts of enhancing performance of current chips are still continuing. Operating systems based on the BTRON and ITRON specifications now run on these chips, which revealed superiority of the TRON instruction set architecture. A compatibility issue arising from `single architecture multiple implementation´ approach specific to TRON project is to be solved by a compatibility validation suite. Next generation VLSI chips are being developed adopting such a parallel execution scheme as super scalar
Keywords
formal specification; instruction sets; microprocessor chips; operating systems (computers); real-time systems; BTRON; ITRON; Real-Time Operating System Nucleus; TRON architecture; instruction set architecture; microprocessor chips; next generation VLSI chips; parallel execution scheme; single architecture multiple implementation; specifications; super scalar; Bandwidth; Electronics industry; Hardware; Microcomputers; Microprocessor chips; Operating systems; Proposals; Silicon; Switches; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
TRON Project Symposium, 1991. Proceedings., Eighth
Conference_Location
Tokyo
ISSN
1063-6749
Print_ISBN
0-8186-2475-2
Type
conf
DOI
10.1109/TRON.1991.213105
Filename
213105
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