A Fault Simulation Methodology for VLSI

Some deficiencies of existing simulators in the context of VLSI design and testing are considered. A fault simulation approach based on CSA (connector-switch-attenuator) theory is defined which overcomes many of these deficiencies. The CSA circuit elements and logic values needed to model combinational circuits are described and applied to the analysis of various types of MOS circuits. A charge-storage element called a well is introduced to simulate sequential behavior. It is shown that many fault types, including stuck-line faults, short circuits, open circuits, and delay faults can be modeled in a uniform and efficient manner.