Reliable On-Chip Memory Design for CMPs

Author

BanaiyanMofrad, Abbas

Author_Institution

Center for Embedded Comput. Syst., Univ. of California, Irvine, Irvine, CA, USA

fYear

2012

fDate

8-11 Oct. 2012

Firstpage

487

Lastpage

488

Abstract

Aggressive technology scaling in deep sub micron regime makes chips more susceptible to failures. This causes multiple realibility challenges in the design of modern chips, including manufacturing defects, wear-out, and parametric variations. With increasing area occupied by different on-chip memories in modern computing platforms such as Chip Multi-Processors (CMPs), memory reliability becomes a challenging issue. Traditional on-chip memory reliability techniques (e.g., ECC) incur significant power and performance overheads. To tackle such challenges, my research introduces several designs for fault-tolerance of both L1 and L2 cache memories in uni-core processors [1], Last-level Cache (LLC) in CMPs [3][4], and LLC in Networks-on-Chip (NoCs) [2].

Keywords

cache storage; failure analysis; fault diagnosis; fault tolerant computing; integrated circuit design; integrated circuit reliability; microprocessor chips; multiprocessing systems; network-on-chip; CMP; ECC; L1 cache memory; L2 cache memory; LLC; NoC; aggressive technology scaling; chip failure; chip multiprocessor; deep submicron regime; fault-tolerance; last-level cache; manufacturing defect; modern computing platform; networks-on-chip; on-chip memory reliability technique; parametric variation; performance overhead; power overhead; realibility; reliable on-chip memory design; unicore processor; wear-out; Fault tolerant systems; Multicore processing; Redundancy; Reliability engineering; System-on-a-chip; CMP; On-chip memory; Reliability;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliable Distributed Systems (SRDS), 2012 IEEE 31st Symposium on

Conference_Location

Irvine, CA

ISSN

1060-9857

Print_ISBN

978-1-4673-2397-0

Type

conf

DOI

10.1109/SRDS.2012.60

Filename

6424904