Application specific processor for multi-standard video decoding

Application-specific instruction processor is a new design methodology to develop optimized processors for specific applications. This paper proposes a new application-specific instruction processor and compiler for multi-standard video decoding. They are based on the 6-stage pipelined dual issue VLIW+SIMD architecture, efficient instructions for multi-standard video decoding, and compiler mapping techniques such as CKF(compiler known function) and inline assembly. SMIC 130nm process is used for implementation of the proposed architecture whose approximate gate count is about 130K and runs at 125MHz. Compared to the existing ARM processor, the proposed architecture and compiler result in about 20% improvement in video decoding in terms of total cycles as well as smaller hardware complexity.