A ΔΣ ADC using 4-bit SAR type quantizer for audio applications

This paper presents a second-order delta-sigma modulator for audio applications. It uses feed-forward architecture and 4-bit quantizer to enhance linearity and noise performance. A 4-bit successive approximation (SAR) analog-to-digital converter (ADC) with summing operation is implemented to reduce power consumption by eliminating the active summing amplifier. In order to reduce the distortion resulted from the capacitor mismatch of the feedback digital-to-analog converter (DAC), a tree-structured dynamic element matching (DEM) is employed. The prototype delta-sigma ADC implemented in a 45 nm CMOS process occupies 231.2 μm² and achieves a dynamic range (DR) of 94.0 dB, a peak signal-to-noise ratio (SNR) of 92.1 dB and a peak signal-to-noise and distortion ratio (SNDR) of 84.5 dB for 24 kHz signal bandwidth, while consuming 8.2 mW with 3.3 V supply.