A 6 bit linear binary RF DAC in 0.25µm SiGe BiCMOS for communication systems

Author

Khafaji, Mahdi ; Gustat, Hans ; Scheytt, Christoph

Author_Institution

IHP Microelectron., Frankfurt (Oder), Germany

fYear

2010

fDate

23-28 May 2010

Firstpage

916

Lastpage

919

Abstract

This paper presents a circuit technique to improve the frequency domain behavior of the binary weighted digital to analog convertors (DAC). It is shown that by adding a current buffer stage, the effect of one of the major drawbacks in this architecture, the impedance variation in every stage, is reduced. To verify the method, a fully binary 6 bit 20.5 Gsps DAC with 1 W power dissipation and measured SFDR higher than 28.2 dBc up to 6.2 GHz input bandwidth was fabricated. The DAC produces 1 Vpp differential output, and less than 60 ps full scale rise time.

Keywords

BiCMOS integrated circuits; Ge-Si alloys; buffer circuits; digital-analogue conversion; radiofrequency integrated circuits; wide band gap semiconductors; SiGe; SiGe BiCMOS; binary weighted digital to analog convertors; buffer circuits; communication systems; impedance variation; linear binary RF DAC; power 1 W; power dissipation; voltage 1 V; word length 6 bit; Bandwidth; BiCMOS integrated circuits; Converters; Frequency domain analysis; Germanium silicon alloys; Impedance; Power dissipation; Power measurement; Radio frequency; Silicon germanium; BiCMOS integrated circuits; Digital to analog convertor; Nyquist rate DAC; buffer circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Symposium Digest (MTT), 2010 IEEE MTT-S International

Conference_Location

Anaheim, CA

ISSN

0149-645X

Print_ISBN

978-1-4244-6056-4

Electronic_ISBN

0149-645X

Type

conf

DOI

10.1109/MWSYM.2010.5517724

Filename

5517724