An efficient GPIO block design methodology using formalized SFR description

Recently, the size and complexity of a GPIO block, which implements IO paths for off-chip communications, have been increased significantly, so the possibility of making human errors in designing GPIO block has been increased. It is difficult to enhance GPIO design productivity because the architecture of Special Function Register (SFR) for GPIO block and multi-IO paths are fixed at relatively late stage of design activities in general. GPIO design also varies according to the designer, fabrication technology and product family, which makes design reuse difficult. This paper shows our analysis of the characteristics of SFRs in GPIO block, and a set-up of the methodology to formalize descriptions of specification to express various GPIO SFR architectures, and finally, design automation of the GPIO block. The experimental result shows that it is possible to describe various GPIO architectures with the proposed description methodology. In our case study, we succeeded on designing a GPIO block in a SOC platform which has more than 300 GPIO pins and 1,000 PAD pins. As a result, the amount of manual description for generating the GPIO block was reduced by 98%, compared to the traditional RTL description.