Considerations on system-level behavioural and structural modeling extensions to VHDL

Author

Ashenden, Peter J. ; Wilsey, Philip A.

Author_Institution

Dept. of Comput. Sci., Adelaide Univ., SA, Australia

fYear

1998

fDate

16-19 Mar 1998

Firstpage

42

Lastpage

50

Abstract

This paper reviews the requirements on a language for modeling behaviour and structure at the system level, and considers possible approaches to extending VHDL to meet these requirements. Modeling issues in a system-level design language are identified, including abstraction of data, concurrency, communication and timing, and design refinement. Some system-level design languages and notations are surveyed, and previous proposals to extend VHDL for system-level design are reviewed. Specific language design issues for extending VHDL are discussed, and some alternative solutions are presented

Keywords

digital simulation; hardware description languages; logic CAD; VHDL; communication; concurrency; data abstraction; design refinement; language requirements; system-level behavioural modeling; system-level design language; system-level structural modeling; timing; Computer science; Concurrent computing; Embedded software; Energy consumption; Hardware design languages; Packaging; Proposals; System-level design; Timing; Unified modeling language;

fLanguage

English

Publisher

ieee

Conference_Titel

Verilog HDL Conference and VHDL International Users Forum, 1998. IVC/VIUF. Proceedings., 1998 International

Conference_Location

Santa Clara, CA

ISSN

1085-9403

Print_ISBN

0-8186-8415-1

Type

conf

DOI

10.1109/IVC.1998.660679

Filename

660679