DocumentCode
3146055
Title
Verilog nonblocking assignments demystified
Author
Cummings, Clifford E.
Author_Institution
Sunburst Design Inc., Beaverton, OR, USA
fYear
1998
fDate
16-19 Mar 1998
Firstpage
67
Lastpage
69
Abstract
Nonblocking assignments are an important construct to accurately model hardware both for behavioral and RTL simulation; however, there are many misunderstandings surrounding how nonblocking assignments work. This paper examines many of the misunderstandings surrounding nonblocking assignments and how nonblocking assignments are appropriately used in behavioral and RTL-synthesis modeling
Keywords
hardware description languages; RTL simulation; RTL-synthesis modeling; Verilog nonblocking assignments; behavioral simulation; Discrete event simulation; Displays; Hardware design languages; Permission; Raw materials; Web pages;
fLanguage
English
Publisher
ieee
Conference_Titel
Verilog HDL Conference and VHDL International Users Forum, 1998. IVC/VIUF. Proceedings., 1998 International
Conference_Location
Santa Clara, CA
ISSN
1085-9403
Print_ISBN
0-8186-8415-1
Type
conf
DOI
10.1109/IVC.1998.660682
Filename
660682
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