Developing through-silicon stacking process using 3-D CMOS imager as a test vehicle

We present a three-dimensional (3-D) CMOS imager to be used as a process development vehicle for through-silicon stacking. The 3-D CMOS imager comprises three tiers: CMOS image sensor (CIS), analog-to-digital converter (ADC), and image signal processor (ISP), all in a form of array implementation. The CIS tier contains a 2048 × 1536 backside illuminated pixel array, the ADC tier contains a 16 × 8 successive approximation register (SAR) ADC array, and the ISP tier contains a 4 × 2 parallel architecture core (PAC) array. The die stack employs both face-to-face and face-to-back bonding schemes. TSMC 0.18 μm 1P6M CIS process is used for device wafers; through-silicon via (TSV), formed after CMOS and from the front side of the wafer, is used for the post-foundry process performed at ITRI. The TSV diameter is 30 μm and the micro-bump pitch is 60 μm The target substrate thickness of the wafer varies from 5 μm for the CIS tier, 50 μm for the ADC tier, to 725 μm for the ISP tier.