Physical hierarchy exploration of 3D processors

Most of the existing 3D designs restrict each functional module in the logical hierarchy to be on a single die, which may not generate the best 3D physical hierarchy. However, a flat 3D implementation will greatly increase the design complexity. Therefore, it is worthwhile to apply virtual 3D physical design methods for design planning at the early-design stage, instead of only performing floorplanning with existing 2D modules. In general, we are motivated to use a 3D placer to explore the benefits of removing the logical hierarchical restrictions at the early-design stage. We perform some experiments on the design planning of the LEON3 processor. Compared to a flat 3D design, planning the entire processor core on a single die brings in 10% longer wirelength, and planning the entire register file on a single die brings in 20% longer wirelength. The results help the quantitative analysis on the tradeoff between the design complexity and the cost of wirelength.