• DocumentCode
    3147034
  • Title

    Tolerating hard faults in microprocessor array structures

  • Author

    Bower, Fred A. ; Shealy, Paul G. ; Ozev, Sule ; Sorin, Daniel J.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
  • fYear
    2004
  • fDate
    28 June-1 July 2004
  • Firstpage
    51
  • Lastpage
    60
  • Abstract
    In this paper, we present a hardware technique, called self-repairing array structures (SRAS), for masking hard faults in microprocessor array structures, such as the reorder buffer and branch history table. SRAS masks errors that could otherwise lead to slow system recoveries. To detect row errors, every write to a row is mirrored to a dedicated "check row". We then read out both the written row and check row and compare their results. To correct errors, SRAS maps out faulty array rows with a level of indirection.
  • Keywords
    arrays; fault tolerant computing; microprocessor chips; system recovery; branch history table; error masking; hard fault masking; hard fault tolerance; microprocessor array structures; reorder buffer; self-repairing array structures; system recovery; Circuit faults; Error correction codes; Fault detection; Hardware; Intelligent networks; Microprocessors; Pipelines; Protection; Random access memory; Redundancy;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Dependable Systems and Networks, 2004 International Conference on
  • Print_ISBN
    0-7695-2052-9
  • Type

    conf

  • DOI
    10.1109/DSN.2004.1311876
  • Filename
    1311876