Polycyclic vector scheduling vs. chaining on 1-port vector supercomputers

The impact of chaining and several instruction scheduling schemes on one-memory-port vector supercomputers, illustrated by the Cray-1 and Cray-2, is studied. The lack of instruction chaining in the Cray-2 vector processor requires a different instruction scheduling scheme from that of the Cray-1. Situations are characterized in which simple vector scheduling can generate optimal code that fully utilizes at least one functional unit for machines with chaining. With enough registers, polycyclic vector scheduling guarantees full utilization of one functional unit after an initial transient, even without chaining, for loops with acyclic dependence graphs. Workloads are represented by vectorizable Livermore Fortran kernels (LFKs). The effectiveness of applying polycyclic scheduling to the Cray-2 is compared with optimal simple vector scheduling on the Cray-1. The speedup of polycyclic vector scheduling on the Cray-2 over the schedule achieved by the current CFT77 compiler on several vectorizable LFKs is presented