DocumentCode
3148070
Title
A New Statistical Model for Gate Array Routing
Author
Gamal, Abbas El ; Syed, Zahir A.
Author_Institution
Information Systems Lab., Stanford University, Stanford, CA.
fYear
1983
fDate
27-29 June 1983
Firstpage
671
Lastpage
674
Abstract
A new statistical model for routing of gate arrays is described. The model takes into consideration the effect of gate utilization of wiring area requirement. Model computed wiring area estimates suggest that it is better (in terms of area and wire length) to use higher utilization and a relatively large number of tracks than low utilization and smaller number of tracks. This is shown to be consistent with the results of two experiments.
Keywords
CMOS technology; Circuit testing; Distributed computing; Equations; Length measurement; Pins; Predictive models; Probability; Routing; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1983. 20th Conference on
ISSN
0738-100X
Print_ISBN
0-8186-0026-8
Type
conf
DOI
10.1109/DAC.1983.1585727
Filename
1585727
Link To Document