Highly robust ultra-thin gate dielectric for giga scale technology

Author

Khare, Manish ; Wang, X.W. ; Ma, T.P.

Author_Institution

Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA

fYear

1998

fDate

9-11 June 1998

Firstpage

218

Lastpage

219

Abstract

This paper focuses on the reliability of ultra-thin (<2.0 nm) jet-vapor deposited (JVD) silicon nitride as an advanced gate dielectric under high-field, high-current stress conditions. The data indicate high breakdown strengths, almost no stress-induced leakage current after passing over 400 C/cm/sup 2/ at high fields, and very little trap generation. Results from TDDB experiments suggest that, for a 10-year lifetime, an electric field of over 8 MV/cm at room temperature and over 6 MV/cm at 150/spl deg/C may be used.

Keywords

CMOS integrated circuits; VLSI; dielectric thin films; electric breakdown; high field effects; integrated circuit reliability; silicon compounds; vapour deposited coatings; 10 year; 150 C; 2 nm; Si/sub 3/N/sub 4/; TDDB experiments; giga scale technology; high breakdown strengths; high-current stress conditions; high-field conditions; jet-vapor deposited dielectric; robust ultra-thin gate dielectric; trap generation; Annealing; Breakdown voltage; Dielectrics; Electric breakdown; Leakage current; Robustness; Silicon; Stress; Substrates; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1998. Digest of Technical Papers. 1998 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-4770-6

Type

conf

DOI

10.1109/VLSIT.1998.689263

Filename

689263