Towards a self-reconfigurable embedded processor architecture

Embedded processors with fixed architecture have disadvantages: they are neither reusable nor are they flexible enough to match the specific needs of different application domains. The main technique employed to accelerate instruction execution in such processors is to add fixed hardware units, which may be useless for some applications yet insufficient for others. This additional hardware may affect area and power constraints badly. A self-reconfigurable architecture would be more flexible as the extended hardware execution units can be reconfigured or replaced at runtime to accelerate more than one algorithm avoiding area, power, and routing problems. Allowing the processor to replace at runtime, unnecessary acceleration execution units with others necessary depending on runtime profiling information, results in significant performance gains with only marginal increase in area and power. As proof of concept, in this paper we show that a significant execution time reduction of approximately 42.5% and a 37% reduction in executed instruction count are achievable for the ¿RGB to CMYK Conversion¿ benchmark, at the cost of a 20% increase in area, using the techniques described here. This preliminary investigation also indicates that, although power increases due to the additional hardware acceleration units employed, significant overall energy savings can be achieved (37.7% in our case study). These results were obtained using Tensilica´s Technology Tools.