DocumentCode
3150413
Title
Delay and Power Optimization in VLSI Circuits
Author
Glasser, Lance A. ; Hoyte, Lennox P J
Author_Institution
Electrical Engineering and Computer Science Department and the Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA
fYear
1984
fDate
25-27 June 1984
Firstpage
529
Lastpage
535
Abstract
The problem of optimally sizing the transistors in a digital MOS VLSI circuit is examined. Macro-models are developed and new theorems on the optimal sizing of the transistors in a critical path are presented. The results of a design automation procedure to perform the optimization is discussed.
Keywords
Circuit optimization; Delay; Laboratories; Large scale integration; MOS devices; Macrocell networks; Power engineering computing; Programmable logic arrays; Silicon; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1984. 21st Conference on
ISSN
0738-100X
Print_ISBN
0-8186-0542-1
Type
conf
DOI
10.1109/DAC.1984.1585848
Filename
1585848
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