Cell-aware analysis for small-delay effects and production test results from different fault models

Author

Hapke, F. ; Schloeffel, J. ; Redemund, W. ; Glowatz, A. ; Rajski, J. ; Reese, M. ; Rearick, J. ; Rivers, J.

Author_Institution

Mentor Graphics, Hamburg, Germany

fYear

2011

fDate

20-22 Sept. 2011

Firstpage

1

Lastpage

8

Abstract

This paper focuses on a new approach to significantly improve the overall defect coverage for CMOS-based designs with the final goal to eliminate any system-level test. This methodology describes the pattern generation flow for detecting cell-internal small-delay defects caused by cell-internal resistive bridges. Results have been evaluated on 1,900 library cells of a 32-nm technology. First production test results are presented from evaluating additional defect detections achieved with different fault models on a 45-nm design.

Keywords

CMOS integrated circuits; automatic test pattern generation; delays; fault diagnosis; integrated circuit design; integrated circuit testing; production testing; CMOS-based designs; cell-aware analysis; cell-internal resistive bridges; cell-internal small-delay defects; defect coverage; fault models; pattern generation flow; production test; size 32 nm; size 45 nm; system-level test; Bridge circuits; Bridges; Delay; Libraries; Logic gates; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference (ITC), 2011 IEEE International

Conference_Location

Anaheim, CA

ISSN

1089-3539

Print_ISBN

978-1-4577-0153-5

Type

conf

DOI

10.1109/TEST.2011.6139151

Filename

6139151