• DocumentCode
    3151773
  • Title

    Macromodeling of Digital MOS VLSI Circuits

  • Author

    Matson, Mark D.

  • Author_Institution
    Research Laboratory of Electronics, Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology
  • fYear
    1985
  • fDate
    23-26 June 1985
  • Firstpage
    144
  • Lastpage
    151
  • Abstract
    This paper presents a method for modeling MOS combinational logic gates. Analyses are given for power consumption, output response delay, output response waveshape, and input capacitance. The models are both computationally efficient and accurate, typically lying within 5% of SPICE estimates. They are pertinent to simulation and optimization applications. A general macromodeling software support package is described. A related paper [1] discusses a circuit optimizer based on these models.
  • Keywords
    Application software; Capacitance; Circuit simulation; Computational modeling; Energy consumption; Logic gates; Propagation delay; SPICE; Software packages; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation, 1985. 22nd Conference on
  • ISSN
    0738-100X
  • Print_ISBN
    0-8186-0635-5
  • Type

    conf

  • DOI
    10.1109/DAC.1985.1585926
  • Filename
    1585926
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3151773