DocumentCode
3153010
Title
Test Structures Utilizing High-Precision Fast Testing For 32nm Yield Enhancement
Author
Karthikeyan, Muthu ; Medina, Louis ; Shiling, Ernesto
Author_Institution
IBM Syst. & Technol. Group, Hopewell Junction, NY
fYear
2009
fDate
March 30 2009-April 2 2009
Firstpage
124
Lastpage
129
Abstract
We describe the development and use of various test structures for 32 nm yield enhancement. These DC defect test structures are tested in parallel mode on a functional tester using special V/I and Pico-Amp measurement cards. This new test method provides measurement accuracy as high as plusmn10 pA along with up to 9times reduction in test time over conventional parametric testing. The large critical area enables reliable estimation of defect densities by failure mechanism.
Keywords
integrated circuit testing; DC defect test structures; failure mechanism; high-precision fast testing; measurement accuracy; test structures; yield enhancement; Cleaning; Current measurement; Current supplies; Density measurement; Electrical resistance measurement; Fluid flow measurement; Indexing; System testing; Time measurement; Voltage; Defect limited yield; Parallel test; Process characterization; Yield enhancement;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronic Test Structures, 2009. ICMTS 2009. IEEE International Conference on
Conference_Location
Oxnard, CA
Print_ISBN
978-1-4244-4259-1
Type
conf
DOI
10.1109/ICMTS.2009.4814624
Filename
4814624
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