• DocumentCode
    3153361
  • Title

    Efficient Netlist Comparison Using Hierarchy and Randomization

  • Author

    Tygar, J.D. ; Ellickson, Ron

  • Author_Institution
    Aiken Computation Lab., Harvard U., Cambridge, MA
  • fYear
    1985
  • fDate
    23-26 June 1985
  • Firstpage
    702
  • Lastpage
    708
  • Abstract
    Programs to compare the layout of ICs with their schematics have recently appeared. These programs have limited functionality and require large amounts of CPU time. We discuss the implementation of a fast [O(n(log n) 2)] logic comparison algorithm which uses hierarchy and randomization. This algorithm handles swappable components without performance degradation and is extremely robust in the presence of input errors. We include experimental data.
  • Keywords
    Algorithm design and analysis; Central Processing Unit; Circuit faults; Data mining; Degradation; Error correction; Integrated circuit layout; Logic; Program processors; Robustness;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation, 1985. 22nd Conference on
  • ISSN
    0738-100X
  • Print_ISBN
    0-8186-0635-5
  • Type

    conf

  • DOI
    10.1109/DAC.1985.1586019
  • Filename
    1586019
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3153361