Charge trapping of ultra-thin ZrHfOx/RuOx/ZrHfOx high-k stacks

Charge trapping in ultra-thin ZrHfO_x/RuO_x/ZrHfO_x high-k stacks has been investigated. ZrHfO_x/RuO_x/ZrHfO_x tri-layer may be a more proper high-k dielectric than ZrHfO_x, because of its smaller equivalent oxide thickness, leakage current and relaxation current. Positive charges trapped in both bulk and interface contribute to the interface state generation and V_fb, shift when electrons are injected from the gate under a negative gate bias condition; meanwhile no noticeable electron or neutral traps created by anode hole degrade much the performance of TiN/ ZrHfO_x/RuO_x/ZrHfO_x/p-Si. It was also observed that a negligible number of defects are generated until the gate bias stress increases to a certain level. The stress-induced trap generation is not reversible and the number of these newly generated traps could be comparable to or even larger than that of the pre-existed ones.