DocumentCode
3154147
Title
A reliability study in P-channel punchthrough for ASIC CMOS input/output buffer leakage
Author
Spory, Erick M.
Author_Institution
Atmel Corp., Colorado Springs
fYear
2007
fDate
15-18 Oct. 2007
Firstpage
139
Lastpage
142
Abstract
Quite simply, does CMOS punchthrough leakage current present a reliability risk? Does this form of leakage accelerate any other failure mechanisms or alter device performance within the circuit? This paper empirically answers these questions while providing an academic understanding of the mechanism and why it dose not pose a reliability risk.
Keywords
CMOS integrated circuits; application specific integrated circuits; integrated circuit reliability; leakage currents; ASIC CMOS leakage current; failure mechanism; p-channel punchthrough; reliability study; Acceleration; Application specific integrated circuits; Driver circuits; Failure analysis; Leakage current; MOSFETs; Springs; Testing; Threshold voltage; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Reliability Workshop Final Report, 2007. IRW 2007. IEEE International
Conference_Location
S. Lake Tahoe, CA
ISSN
1930-8841
Print_ISBN
978-1-4244-1771-9
Electronic_ISBN
1930-8841
Type
conf
DOI
10.1109/IRWS.2007.4469241
Filename
4469241
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