Switching activity estimation using limited depth reconvergent path analysis

We describe a method of polynomial simulation to calculate switching activities in a general-delay combinational logic circuit. This method is a generalization of the exact signal probability evaluation method due to Parker and McCluskey, which as been extended to handle temporal correlation and arbitrary transport delays. Our method is parameterized by a single parameter l, which determines the speed-accuracy tradeoff. l indicates the depth in terms of logic levels over which spatial signal correlation is taken into account. This is done by only taking into account reconvergent paths whose length is at most l. The rationale is that ignoring spatial correlation for signals that reconverge after many levels of logic introduces negligible error. We present results that show that the error in the switching activity and power estimates is very small even for small values of l. In fact, for most of the examples we tried, power estimates with l=1 are within 5% of the exact. However, this error can be higher than 20% for some examples, More robust estimates are obtained with l=2, providing a good compromise between speed and accuracy.