• DocumentCode
    315645
  • Title

    Fully depleted CMOS/SOI device design guidelines for low power applications

  • Author

    Banna, Srinivasa R. ; Chan, Philip C.H. ; Chan, Mansun ; Fung, Samuel K H ; Ko, Ping K.

  • Author_Institution
    Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, Hong Kong
  • fYear
    1997
  • fDate
    18-20 Aug. 1997
  • Firstpage
    301
  • Lastpage
    306
  • Abstract
    In this paper we report the fully depleted CMOS/SOI device design guidelines for low power application. Optimal technology, device and circuit parameters are discussed and compared with bulk CMOS based design. The differences and similarities are summarized. We believe this is the first such study to be reported.
  • Keywords
    CMOS integrated circuits; integrated circuit design; silicon-on-insulator; fully depleted CMOS/SOI device design; low power circuit; CMOS technology; Capacitance; Circuits; Delay; Design engineering; Guidelines; Inverters; Permission; Power engineering and energy; Ultra large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Low Power Electronics and Design, 1997. Proceedings., 1997 International Symposium on
  • Conference_Location
    Monterey, CA, USA
  • Print_ISBN
    0-89791-903-3
  • Type

    conf

  • Filename
    621303
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=315645