DocumentCode
315720
Title
High-speed VLSI design of the LZ-based data compression
Author
Chen, Chun-Te ; Cheni, Liang-Gee
Author_Institution
Ta-Hwa Coll. of Commerce & Technol., Taiwan, China
Volume
3
fYear
1997
fDate
9-12 Jun 1997
Firstpage
2064
Abstract
In this paper, a high-speed VLSI design of the LZ-based data compression is presented. The proposed block processing architecture provides 100 percent hardware utilization and a shorter cycle time for searching the maximum matching strings. A systematic method to find the sharing substructure among the block structures is also proposed. With this systematic method, it can shrink the final area requirement on a single chip for on-line data compression. Hence, the proposed design is more area-efficient than the previous systolic designs
Keywords
VLSI; block codes; data compression; integrated circuit design; parallel architectures; redundancy; LZ-based data compression; area-efficient design; block processing architecture; cycle time; final area requirement; high-speed VLSI design; lossless data compression; sharing substructure; Algorithm design and analysis; Buffer storage; Data compression; Dictionaries; Encoding; Hardware; Pipelines; Signal design; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
Print_ISBN
0-7803-3583-X
Type
conf
DOI
10.1109/ISCAS.1997.621562
Filename
621562
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