Performance optimization of LUT of subthreshold FPGA in deep submicron

Field programmable gate array (FPGA) consumes significant dynamic and static power consumption due to the presence of additional logic for flexibility compared to application specific integrated circuits (ASICs). The cost of ASICs is rising exponentially in deep submicron and hence it is important to investigate ways of reducing FPGA power consumption so that they can also be employed in place of ASICs in portable energy constrained applications. It is also important to investigate the possibility of extending the use of FPGA even in subthreshold region for ultra low power applications. At the same frequency, subthreshold circuits show orders of magnitude power saving over super-threshold circuits for low throughput applications. This paper explores the subthreshold performance of a basic FPGA building block-a Look up Table (LUT). It presents comparative analysis of different topologies of three input LUT in deep submicron (DSM) for delay, power dissipation and switching energy. The proposed cross-coupled PMOS (CCP) encoded LUT shows 36% improvement in delay and 31% in switching energy at the cost of 4% increase in static power dissipation over conventional one. However, the increase in static power consumption is negligible compared to the improvement in switching energy. Thereafter, this paper investigates the potential of carbon nanotube field effect transistor (CNFET) based LUT in the subthreshold region.