Interconnect-aware design methodology for analog and mixed signal design in silicon based technologies using high bandwidth on-chip transmission lines

This paper discusses a new interconnect-aware AMS design methodology which leads to better designs, and is in many ways superior to the RLC post-layout extraction approach. This methodology uses high bandwidth on-chip transmission lines (T-lines) for critical interconnect. The T-lines have been designed for multi-layered metallization stack high speed silicon based technologies, such as the silicon germanium (SiGe) technology, as well as for high speed CMOS technologies.