A tessellator based on a vertex shader for bandwidth-efficient mobile 3D graphics

Author

Chung, Kyusik ; Yu, Chang-Hyo ; Kim, Donghyun ; Kim, Lee-Sup

Author_Institution

Dept. of EECS, KAIST, Daejeon

Volume

03

fYear

2008

fDate

24-25 Nov. 2008

Abstract

A tessellation-enabled shader (TES), 1/250 memory bandwidth saving geometry processor, is proposed for a mobile 3D graphics engine. On-chip vertex generation of tessellation is implemented with 6.2% additional logic gate to a conventional vertex shader. An optimized vector dot product unit, a slim special function unit, and a unified data fetch unit reduce 25.6% of area. Dual-core of TES is fabricated using 0.18 um CMOS technology and processes 120 Mvertices/s at 100 MHz while consuming 272 mW of power.

Keywords

CMOS integrated circuits; computer graphics; logic gates; multiprocessing systems; vector processor systems; CMOS technology; frequency 100 MHz; geometry processor; logic gate; memory bandwidth; mobile 3D graphics; on-chip vertex generation; optimized dot product unit; power 272 mW; slim special function unit; tessellation-enabled shader; unified data fetch unit; vertex shader; Bandwidth; CMOS technology; Computer architecture; Delay; Engines; Geometry; Graphics; Logic gates; Mobile computing; Polynomials; 3D graphics; geometry processor; memory bandwidth; tessellation; vertex shader;

fLanguage

English

Publisher

ieee

Conference_Titel

SoC Design Conference, 2008. ISOCC '08. International

Conference_Location

Busan

Print_ISBN

978-1-4244-2598-3

Electronic_ISBN

978-1-4244-2599-0

Type

conf

DOI

10.1109/SOCDC.2008.4815753

Filename

4815753